Senior FPGA Engineer

10 hours ago

Sydney, New South Wales, Australia ProFound People Full time $120,000 - $180,000 per year

Senior / Principal FPGA Engineer | Sydney | RTL Design, Ultra-low-latency, Verilog

We're partnering with a globally recognised technology firm that has built its reputation on proprietary systems and world-class engineering. They're looking at bringing in experienced FPGA Engineers who can elevate the team's capabilities beyond coding to spec — providing foresight, leadership, and long-term design thinking.

Senior FGPA Engineer Requirements

  • Design, implement, and optimise FPGA solutions for high-speed data handling and execution pipelines.
  • Work on RTL design (Verilog/SystemVerilog) for high-performance digital systems, focusing on deterministic latency.
  • Contribute to ASIC design considerations for long-term ultra-low-latency performance.
  • Apply knowledge of SDH and high-reliability networking in FPGA-based systems.
  • Lead projects and initiatives, setting technical direction, and ensuring long-term scalability.
  • Balance immediate requirements with forward-looking design choices that benefit the company's future growth.

Senior FPGA Engineer Requirements

  • Strong experience in FPGA development (Verilog/SystemVerilog, RTL design).
  • Background in ultra-high-speed systems, ideally in environments requiring low-latency or high-accuracy processing, but experience in other high-performance hardware domains (telecoms, networking, aerospace, etc.) is also valuable.
  • Experience with ASIC design flows or integration is highly valued.
  • Strong problem-solving skills, with the ability to operate in ambiguous environments and break down complex problems into long-term solutions.
  • Demonstrated experience in leading projects/initiatives, not just coding to spec.

This is a very unique environment at a very reputable, globally recognised company. If interested, please apply with your most up-to-date CV & I'll be in touch.

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