
Researcher in FPGA-based AI Hardware Acceleration
2 days ago
Organisation/Company UNIVERSITY OF SYDNEY Research Field Computer science Researcher Profile Leading Researcher (R4) Country Australia Application Deadline 14 Sep :00 (UTC) Type of Contract Other Job Status Full-time Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No
Offer Description- Full time, fixed term for 12 months
- Opportunity to advance research in AI Hardware Acceleration
- Base Salary $89,831 - $121, % superannuation
About the opportunity
The School of Electrical and Computer Engineering at the University of Sydney is seeking to appoint a Research Associate or Postdoctoral Research Associate to contribute to an exciting project focused on the challenge of accelerating ternary neural networks using FPGA devices. The successful candidate will have significant experience in machine learning, FPGA design and an outstanding track record in conducting machine learning research. You will join a team of researchers that are pushing the boundaries of computing. You will have access to our state-of-the-art equipment and facilities and connect with leading researchers worldwide.
Your key responsibilities will be to:
- deliver outcomes in a research project and ensure that milestones are met
- work with colleagues and postgraduates within the project
- prepare materials for publications in journals and conferences
- collaborate with industry partners and leaders in the field of FPGA-based machine learning accelerators
About you
The University values courage and creativity; openness and engagement; inclusion and diversity; and respect and integrity. As such, we see the importance of recruiting talent aligned to these values and are looking for a Researcher in FPGA-based AI Hardware Acceleration who has:
- strong experience in FPGA design, machine learning or a related field
- in the case of the Postdoctoral Research Associate, a PhD (or near completion) in FPGA design, machine learning or a related field
- experience in the development of machine learning models using Python and pytorch
- expertise in two or more of the following technical areas: design of FPGA-based accelerators, high-level synthesis for FPGA design (HLS), quantisation of deep neural networks, large language models (LLMs).
- strong problem solving and analytical skills
Sponsorship / work rights forAustralia
Work Rights: you must have unrestricted work rights in Australia for the duration of this employment to apply. Visa sponsorship is not available for this appointment.
Your employment is conditional upon the completion of all role required pre-employment or background checks in terms satisfactory to the University. Similarly, your ongoing employment is conditional upon the satisfactory maintenance of all relevant clearances and background check requirements. If you do not meet these conditions, the University may take any necessary step, including the termination of your employment.
Applications (including a cover letter, CV, and any additional supporting documentation) can be submitted via the Apply button at the top of the page.
For employees of the University or contingent workers, please login into your Workday account and navigate to the Career icon on your Dashboard. Click on USYD Find Jobs and apply.
For a confidential discussion about the role, or if you require reasonable adjustment or any documents in alternate formats, please contact Rebecca Astar or Cherie Goodwin, Recruitment Operations by email to
The University reserves the right not to proceed with any appointment.
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Sydney, New South Wales, Australia Unist Full timeOrganisation/Company UNIVERSITY OF SYDNEY Research Field Computer science Researcher Profile Leading Researcher (R4) Country Australia Application Deadline 14 Sep 2025 - 00:00 (UTC) Type of Contract Other Job Status Full-time Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position...
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