GPU Performance Optimizer

10 hours ago

Sydney, New South Wales, Australia beBeeArchitect Full time $180,363 - $243,492

We are seeking a highly skilled and experienced GPU Power Architect/Microarchitect to lead our Data Center and Gaming GPU Power Optimization and Modeling efforts. This is a strategic role that requires expertise in processor pipelines, IP blocks at the micro-architectural and RTL level, and innovation execution leadership.

Job Description

This position involves driving power optimization and modeling advances for multi-generational roadmaps to maximize power and cost-constrained performance for AMD graphics platforms. The ideal candidate will work closely with product teams to understand PPA requirements, translate them into requirements for various IP blocks, and evangelize for power efficiency. Key responsibilities include leading a strong DGPU Power Optimization and Modeling team, driving power optimization and modeling advances, working with product teams, guiding the power optimization team and IP implementation teams, and specifying power test plans.

Key Responsibilities
  • Lead a strong DGPU Power Optimization and Modeling team
  • Drive Power Optimization and Modeling advances for multi-generational roadmap to maximize power and cost constrained performance for AMD graphics platforms
  • Work with product teams to understand the PPA requirements, translate those into requirements for various IP blocks, evangelize for power efficiency and drive attainment
  • Guide the power optimization team and IP implementation teams in identifying power optimization opportunities, estimate ROI, and establish plan of record
  • Drive the Architecture, architectural optimization RTL design fixes to deliver the best design for Perf/Watt and Perf/$
  • Specify Power Test Plans at Graphics Subsystem blocks and at Graphics level, review and sign-off on PTPX/Power Artist data readouts
  • Use judgement in projecting dynamic power improvements per IP and for whole SOC, and provide up-leveled readouts to project leadership and executives
  • Lead and provide guidance to team developing IP Power Models of different kinds, and drive correlation to RTL and Silicon at various stages
  • Coach and develop a team of world-class Power Optimization and Modeling engineers

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