Senior IC Design Engineer

1 week ago

Senior South, Australia Palma Ceia SemiDesign Full time $104,000 - $130,878 per year

Required

  • Deep experience in IC design leading to production, production debug, testing support and yield enhancement
  • Experience with RF system architectures, link budgets, trade-offs for key elements such as DC offset calibration loop, IIP2 calibration loop, AGC, etc.
  • RF or analog circuit design for WiFi, LTE, TV or other high dynamic range systems
  • Implementation experience in either 65nm or 40nm
  • At least 7 years at a relevant comm IC house or IDM

Big Plus

  • Experience with leading a team from design concept through project completion
  • Lab and testing experience: spurious debug, noise testing, performance testing
  • Customer-facing exposure: determining specifications, schedule, technical trade-offs

Block Experience (one Or More Would Be Required)

  • LNA, Mixer, VGA, PA driver, IQ modulatorActive filter design,
  • Active filter design, high speed op-amp, log limiter amplifiers, power detectionPLL, integer/fractional loops, PFD,
  • PLL, integer/fractional loops, PFD, high speed divider circuits, VCO, loop filter, PLL system analysis, timing analysis, pre-scalers,High speed DAC design, above 10 bit, above 300MSPS
  • High speed DAC design, above 10 bit, above 300MSPSHigh speed ADC design, (one of or all — pipeline,
  • High speed ADC design, (one of or all — pipeline, SAR and CTSD), above 10 bit, above 80MSPS

Location:

  • McKinney, Texas (preferred)

Additional Information

  • Start Date: Immediate
  • Email resumes to:
  • No calls. EOE.

Palma Ceia SemiDesign announces Silicon-Proven IEEE 802.11ah HaLow Transceiver for Industry-Standard IoT Applications

Palma Ceia Joins Wi-Fi Alliance

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