FPGA Design Engineer

4 days ago

Pyrmont, New South Wales, Australia DroneShield Group Pty Ltd Full time
About the Role

DroneShield is seeking a highly skilled FPGA Engineer to join our team in Sydney, Australia. As a key member of our team, you will be responsible for designing, developing, and implementing FPGA-based systems to support real-time Digital Signal Processing.

Key Responsibilities
  • Design and develop FPGA-based systems for real-time Digital Signal Processing
  • Research and develop highly optimized RTL implementations of DSP, ML, and statistical algorithms
  • Optimize the core of DroneShield's technology for accuracy, performance, stability, and maintenance
  • Scale the R&D, development, verification, and validation infrastructure
Requirements
  • BS/BE degree in Electronic Engineering or similar technical field of study
  • 2+ years of experience working within an established team
  • Strong experience with programming, debugging, and verifying Verilog, VHDL, or SystemVerilog
  • Strong experience using and designing automated Verification and Validation frameworks
  • Experience with synthesis and complex timing closure on resource-constrained FPGAs
  • Experience in high-speed digital design and building customized IP cores
  • FPGA development experience using FPGA software tools such as Vivado, Quartus, Vitis, etc.
  • Experience with designing and implementing high-throughput, low-latency, and fully pipelined FPGA architectures
  • Experience writing C/C++ firmware for FPGA modules along with familiarity with scripting languages (Python)
  • Experience working in a Linux environment
  • Experience working with PCB schematics, board bring-ups, and debugging hardware is highly desirable
  • Strong background and experience in Digital Signal Processing is highly desirable
  • A general RF background and knowledge of RF transmission protocols and general principles is desirable
  • Understanding or working knowledge of Machine Learning (ML) concepts within the scope of FPGA implementation would be ideal

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