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Senior Low-Latency Engineer

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Sydney, New South Wales, Australia beBeeFPGA Full time $180,000 - $200,000
Fast-Trading Expert Wanted

We are seeking a skilled engineer to lead the development of our high-performance trading systems. The ideal candidate will have extensive experience in designing and deploying hardware systems that can process market data, make decisions, and execute trades with ultra-low latency.

The successful candidate will be responsible for architecting, designing, and deploying FPGA-based solutions that meet our business needs. This includes collaborating with traders and developers to translate strategy requirements into real-time hardware logic, analyzing and optimizing system performance at every level, and developing and maintaining a robust simulation and testing framework to ensure system reliability.

In addition, the successful candidate will monitor and improve FPGA performance in live trading environments through benchmarking and profiling, and explore emerging technologies to continually sharpen our hardware advantage.

  • Main Responsibilities:
  • Design and deploy FPGA-based solutions for parsing market data and executing trades with ultra-low latency.
  • Collaborate with traders and developers to translate strategy requirements into real-time hardware logic.
  • Analyze and optimize system performance at every level from transceiver tuning to logic layout.
  • Develop and maintain a robust simulation and testing framework to ensure system reliability.
  • Monitor and improve FPGA performance in live trading environments through benchmarking and profiling.
Key Skills and Experience:

Requirements:

  • 5+ years' experience in financial markets, exchange protocols (FIX, OUCH, ITCH), or co-designing FPGA and software systems.
  • BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
  • Extensive experience with FPGA or ASIC technologies, including proficiency in either VHDL, Verilog, or SystemVerilog.
  • Strong engineering skills in Python, C++ or C.
  • Solid understanding of digital design principles, including pipelining, flow control, and clock domain crossing.
  • Experience with FPGA development tools and toolchains (Vivado, Quartus, Synplify, etc.).
  • Proven ability to optimize for low latency and high throughput in production systems.
  • Familiarity with networking protocols (e.g., Ethernet, TCP, UDP).