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HW Architect and Verification Engineer

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Design Engineer Role

About Morse Micro : Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability.

Job Description:

You will be responsible for designing, integrating, verifying, and bringing up an IEEE 802.11ah PHY to be used in our family of Wi-Fi chips. You'll work closely with the digital, systems, and firmware teams to help architect and verify the PHY, ensuring functional and performance goals are achieved.

Your key responsibilities include:

  • Developing the 802.11ah PHY in Scala (Chisel), System Verilog, and C
  • Functional verification of the 802.11ah PHY in RTL simulators, SDF-annotated gate level simulators, and AMS simulators using SystemVerilog, Verilog-A, Matlab, C, and Python
  • Collaborating with the Systems team to achieve optimal performance
  • Working closely with the Analog & RF team to define and improve radio interface
  • Assisting with bring-up of silicon in the lab and debugging PHY performance

To succeed in this role, you should have a solid understanding of digital signal processing (DSP) , with emphasis on HW implementation and proven experience developing multiple DSP blocks in complex SoCs . Familiarity with the IEEE 802.11 PHY layer and hands-on experience with the Cadence or Synopsys simulation suite are also essential.

Bonus skills such as experience performing PHY bring-up, debug, and performance measurement on silicon in the lab, good understanding of embedded processors, familiarity with RISC-V, solid understanding of mixed signal ASIC design and simulation, experience using the git revision control tool, and experience with development and debugging of digital designs from RTL design through are highly desirable.

Requirements:

Digital Signal Processing (DSP): A solid understanding of DSP, emphasizing HW implementation and experience developing multiple DSP blocks in complex SoCs .

IEEE 802.11 PHY Layer: Familiarity with the IEEE 802.11 PHY layer and hands-on experience with the Cadence or Synopsys simulation suite.

Embedded Processors: Good understanding of embedded processors.

RISC-V: Familiarity with RISC-V.

Mixed Signal ASIC Design: Solid understanding of mixed signal ASIC design and simulation.

Revision Control Tools: Experience using the git revision control tool.

Digital Design Development: Experience with development and debugging of digital designs from RTL design through.

Desirable Skills:

PHY Bring-up and Debug: Experience performing PHY bring-up, debug, and performance measurement on silicon in the lab.

ASIC Simulation: Solid understanding of mixed signal ASIC design and simulation.