Design Verification Engineer

2 weeks ago


Melbourne, Victoria, Australia Apple Inc. Full time
About the Role

We are seeking a highly skilled Design Verification Engineer to join our dynamic team at Apple Inc. As a member of our group, you will have the rare opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day.

Key Responsibilities
  1. Establish and Lead Verification Methodology: Develop and implement a scalable and portable verification environment for IP designs, ensuring bug-free first silicon.
  2. Develop and Execute Verification Plans: Create detailed test and coverage plans based on micro-architecture, drive verification methodology, and execute verification plans for all features under your care.
  3. Develop Verification Environment and Test-Benches: Create verification environment, including stimulus, checkers, assertions, trackers, and coverage, and develop block, IP, and SoC level test-benches.
  4. Track and Report Design Verification Progress: Monitor and report design verification progress using various metrics, including bugs and coverage.
  5. Collaborate with Analog Team: Work closely with the analog team to ensure overall bug-free IP design.
Requirements
  • Technical Expertise: Strong working knowledge of SystemVerilog test-bench language and UVM, experience with verification methodologies and tools, and experience with different DDR protocols.
  • Leadership Experience: Proven experience in a technical lead position, with experience in IP verification methodology for IPs such as PHYs, PLLs, etc.
  • Education and Experience: BS degree in technical discipline with a minimum of 10 years of relevant experience.


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